Intel's next-gen Diamond Rapids "Xeon" CPUs will carry two new and separate tiles codenamed CBB and IMH.
Intel Diamond Rapids "Xeon" CPUs Pack CBB Compute and IMH I/O+IMC Tiles, PCIe Gen6 Support Too
New details of Intel's next-gen Diamond Rapids "Xeon" CPUs have been spotted within Kernel patches. These patches reveal the design philosophy of Intel's upcoming Xeon architecture and how the chips will be made.
For Diamond Rapids, Intel will be introducing two brand new tiles. First, we have CBB "Core Building Block" which will be the compute tile, and the major detail about this is that, unlike Granite Rapids, which added the IMC on the same tile, Diamond Rapids will be separating it.
The IMC or integrated memory controller will be featured on the new IMH "Integrated I/O & Memory Hub" tile. These are separate from the compute tile (CBB), and Diamond Rapids is said to feature up to two of these IMH dies. It is also suggested by @InstLatX64 that the IMH die will be situated on the base tile, similar to how Clearwater Forest does things.
Similar to Intel Sapphire Rapids, Diamond Rapids relies on discovery tables for uncore enumeration. Key differences and additions include:
- DMR may have two Integrated I/O and Memory Hub (IMH) dies, which are separate from the compute tile (CBB) dies. Each CBB die and each IMH die has its own dedicated discovery table.
- Unlike prior CPUs that retrieve the global discovery table portal exclusively through either PCI or MSR, DMR uses PCI for IMH PMON discovery and MSR for CBB PMON discovery
- DMR introduces several new PMON types, including SCA, HAMVF, D2D_ULA, UBR, PCIE4, CRS, CPC, ITC, OTC, CMS, and PCIE6.
- Unlike SPR, IIO free-running counters in DMR are MMIO-based.
Besides this, other details are also mentioned, such as PCIe Gen6 support, which would make sense since the technology has been announced since 2026, and will be making its way to next-gen data center CPU platforms such as Diamond Rapids and Venice this year.
As per previous information, Intel's Diamond Rapids "Xeon" CPUs are expected to feature up to 192 cores, and some rumors even point to up to 256 cores, though Intel hasn't confirmed a lot of details yet. We know that the chips are expected to utilize the latest 18A process node, and the core architecture is going to be Panther Cove P-Cores. Early platform details highlight up to 650W TDPs on the LGA 9324 platform with multi-socket capabilities. Intel is expected to introduce its Diamond Rapids CPUs by the mid- or 2nd half of 2026.
About the author: A Software Engineer by training and a PC enthusiast by passion, Hassan Mujtaba serves as Wccftech's Senior Editor for hardware section. With years of experience in the industry, he specializes in deep-dive technical analysis of next-generation CPU and GPU architectures, motherboards, and cooling solutions. His work involves not only breaking news on upcoming technologies but also extensive hands-on reviews and benchmarking.
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