Intel's next-gen Arrow Lake-S Desktop CPUs might have an edge in terms of Instruction Set support over their mobile Arrow Lake-H siblings.
Intel Arrow Lake Splits ISA Between Arrow Lake Desktop & Arrow Lake Mobile, AVX-VNNI-INT16 & More Missing From Laptop 2nd Gen Core Ultra
According to the 50th Future ISA Guide published by Intel, it looks like the Arrow Lake ISA (Instruction Set Architecture) will vary between desktop and laptop platforms.
The ISA Guide is basically a list of instruction sets that either exist or will be added to a CPU family from Intel. Intel has revealed that the Arrow Lake Desktop CPUs will come with support for a set of instructions such as the AVX-VNNI-INT16, SHA512, SM3, and SM4, along with LBR Event Logging. Now these instruction sets won't feature in Arrow Lake-H CPUs which target the mobility side of things, and while Intel hasn't given an explanation behind the decision, it may have something to do with the usability of the mentioned instructions and the core structure of both families which we will discuss later on.
Speaking of what these individual instructions are, the AVX-VNNI-INT16 is a type of "Vector Neural Network Instructions", which basically aims at making tasks involving deep learning and AI tasks much faster. The exclusion of it in Arrow Lake-H mobile chips would result in a considerably lower performance at genAI workloads versus the Arrow Lake-S parts, but it wouldn't have much of an impact in mainstream applications, hence consumers who aren't into AI shouldn't worry about it.
According to the 50th Future ISA Guide, this time #ArrowLakeH C065x mobile has different ISA than the #ArrowLakeS C066x desktop#AVX_VNNI_INT16, #SHA512, #SM3, #SM4 https://t.co/5nUqDcnoDl pic.twitter.com/Yf1dvLBNOY
— InstLatX64 (@InstLatX64) October 30, 2023
Similarly, SHA512, SM3, and SM4 cryptographic-based instructions, are aimed at speeding up algorithms and enhancing security onboard. Hardware support for these algorithms allows the processor to perform hash calculations and encryption/decryption operations much faster than software-based implementations. There are also some instructions that will be included across all Arrow Lake chips such as CMPCCXADD, AVX-IFMA, AVX-NE-CONVERT, RDMSRLIST, LASS,& UIRET.
A possibility is that Intel's Arrow Lake-S CPUs are only meant to utilize two-core architectures which include Lion Cove for P-Core and Skymont for E-Core while Arrow Lake-H and mobile chips will use a 3-core architecture with Lion Cove for P-Cores, Skymont for E-Cores and Crestmonth for the low-power E-Cores residing on the I/O tile. Since Crestmont doesn't feature support for the latest ISA, the Arrow Lake-H chips won't be taking full advantage of the newest ISA. This goes in line with the previous reports which mentioned Meteor Lake and Arrow Lake chips featuring a very similar VPU and Lunar Lake bringing a major update.
Intel's support for such instructions is never final, since the company tends to add them later on to a particular lineup, hence Arrow Lake mobile CPUs might get the instruction set in the future.
Intel Mobility CPU Lineup:
| CPU Family | Panther Lake | Lunar Lake | Arrow Lake | Meteor Lake | Raptor Lake | Alder Lake |
|---|---|---|---|---|---|---|
| Process Node (CPU Tile) | Intel 18A | TSMC N3B | TSMC N3B | Intel 4 | Intel 7 | Intel 7 |
| Process Node (GPU Tile) | TSMC N3E / Intel 3 | TSMC N3B | TSMC 5nm | TSMC 5nm | Intel 7 | Intel 7 |
| CPU Architecture | Hybrid | Hybrid (Dual-Core) | Hybrid (Triple-Core) | Hybrid (Triple-Core) | Hybrid (Dual-Core) | Hybrid (Dual-Core) |
| P-Core Architecture | Cougar Cove | Lion Cove | Lion Cove | Redwood Cove | Raptor Cove | Golden Cove |
| E-Core Architecture | Darkmont | N/A | Skymont | Crestmont | Gracemont | Gracemont |
| LP E-Core Architecture (SOC) | Darkmont | Skymont | Crestmont | Crestmont | N/A | N/A |
| Top Configuration (Compute Tile) | 4+8 (H-Series) | 4+4 (MX Series) | 6+8 (H-Series) 2+8 (U-Series) | 6+8 (H-Series) 2+8 (U-Series) | 6+8 (H-Series) 8+16 (HX-Series) | 6+8 (H-Series) 8+8 (HX-Series) |
| Max Cores / Threads | 16/16 | 8/8 | 14/14 | 14/20 | 14/20 | 14/20 |
| AI NPU | NPU5 (50 TOPS) | NPU4 (48 TOPS) | NPU3.5 (13 TOPS) | NPU3 (11 TOPS) | NPU2 (7 TOPS) | NPU2 (7 TOPS) |
| Planned Lineup | Core Ultra 300 | Core Ultra 200V | Core Ultra 200 | Core Ultra 100 | 14th/13th Gen | 12th Gen |
| GPU Architecture | Xe3-LPG (Battlemage) | Xe2-LPG (Battlemage) | Xe-LPG+ (Alchemist) | Xe-LPG (Alchemist) | Iris Xe (Gen 12) | Iris Xe (Gen 12) |
| Xe Cores (Max) | 12 Xe3 Cores | 8 Xe2 Cores | 8 Xe Cores | 8 Xe Cores | 96 EUs (768 Cores) | 96 EUs (768 Cores) |
| Memory Support | LPDDR5X-9600 | LPDDR5X-8533 | DDR5-5600 LPDDR5-7500 LPDDR5X-8533 | DDR5-5600 LPDDR5-7400 LPDDR5X - 7400+ | DDR5-5200 LPDDR5-5200 LPDDR5-6400 | DDR5-4800 LPDDR5-5200 LPDDR5X-4267 |
| Memory Capacity (Max) | 128 GB | 32 GB | 128 GB | 96 GB | 64 GB | 64 GB |
| Thunderbolt Support | TB5 | TB5 | TB5 | TB4 | TB4 | TB4 |
| WiFi Capability | WiFi 7 | WiFi 7 | WiFi 7 | WiFi 6E | WiFi 6E | WiFi 6E |
| TDP | 17-45W | 17-30W | TBD | 7W-45W | 15-55W | 15-55W |
| Launch | 2H 2025 | 2H 2024 | 2H 2024 | 2H 2023 | 1H 2023 | 1H 2022 |
News Source: @InstLatX64
About the author: Muhammad Zuhair is a hardware and technology reporter for Wccftech, specializing in the semiconductor industry and the complex interplay between technology, manufacturing, and geopolitics. His coverage focuses on the corporate strategies and technological roadmaps of industry giants like TSMC, NVIDIA, Samsung, and Intel. Zuhair's expertise lies in deconstructing complex topics such as fabrication nodes (e.g., 2nm process), the economic impact of policies like the CHIPS Act, and the strategic development of AI infrastructure from NVIDIA, AMD and Intel.
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