Intel has revealed progress around the 18A chip at the Tech Tour, and based on what the firm claims, the process is at an all-time low in defect density.
Intel's 18A Defect Density Indicates That Yield Rates Are Optimal For Volume Production
The 18A node is shaping up to be one of the most crucial releases by Intel Foundry since its inception, mainly because this time Intel's chip manufacturing abilities are being scrutinized by both political and business entities, which means that Team Blue needs to ensure a capable end solution. We were expecting details around 18A, and based on what Intel discussed during the ITT keynote, it is disclosed that 18A is currently at its lowest defect density, with volume production on track for Q4.
Now, this is one of the most pivotal aspects for 18A in particular, as it shows the process is shaping up to be competitive in terms of mass production and volume scalability. For those unfamiliar with defect density, it refers to the number of defects per unit area on a chip wafer that may lead to a non-functional product, interfering with transistors, interconnects, and vias that hinder circuit operations. A higher defect density means that larger die sizes are likely to be affected, which isn't optimal for a process like 18A, which is seen as a solution for massive chip packages.
The reason why the defect density is important to be at an 'all-time' low here is that it is a direct indicator of where we can expect yield rates to be. The figures around 18A yield rates have evolved radically over time, with outlets claiming them to be as low as 10%. However, such figures are currently impossible, especially since Intel has decided to ramp up volume manufacturing of the 18A node. Lower defect rates enable Team Blue to support larger die designs, catering to markets such as the HPC segment.
Defect density does not fully represent the entire situation regarding 18A, as other parameters must be considered, such as parametric failures, mask errors, and process margins. However, it is crucial if you want to estimate the production volume around a particular node. Since the IFS has managed to lower defect density by a significant margin, we should expect the chip to be a competitive package, potentially competing with options such as TSMC's N2 or Samsung's SF2 processes.
About the author: Muhammad Zuhair is a hardware and technology reporter for Wccftech, specializing in the semiconductor industry and the complex interplay between technology, manufacturing, and geopolitics. His coverage focuses on the corporate strategies and technological roadmaps of industry giants like TSMC, NVIDIA, Samsung, and Intel. Zuhair's expertise lies in deconstructing complex topics such as fabrication nodes (e.g., 2nm process), the economic impact of policies like the CHIPS Act, and the strategic development of AI infrastructure from NVIDIA, AMD and Intel.
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