Huawei's latest mobile-focused chip, the Kirin 9030, is attracting quite a lot of eyeballs lately, especially as the chip forms a pristine platform for Huawei's HiSilicon and China's SMIC to showcase their technological prowess in the face of Washington's years-long ban on the export of the more advanced EUV lithography tech to China.
The architecture of Huawei's Kirin 9030 and Kirin 9030 Pro
Huawei has just unveiled its Mate 80 and Mate X7 smartphones, powered by the Kirin 9030 and Kirin 9030 Pro chips.
The vanilla Kirin 9030 chip consists of:
- 8x ARMv8 CPU cores with 12 threads, with the prime core clocked at 2.75GHz, the performance cores at 2.27GHz, and the efficiency cores at 1.72GHz.
- Maleoon 935 GPU
Similarly, the Kirin 9030 Pro chip consists of:
- 9x ARMv8 CPU cores with 14 threads in a 1+4+4 core configuration, with the prime core clocked at 2.75GHz, the performance cores at 2.27GHz, and the efficiency cores at 1.72GHz.
- Maleoon 935 GPU
Do note that these figures are based on provisional benchmark tests, with the chips reportedly not running at their full potential.
The Kirin 9030/Pro chips are testing the limits of DUV-based lithography
TechInsights has confirmed that the Kirin 9030 chip is based on SMIC's N+3 fabrication process, which appears to be a step-up from its N+2 second-gen 7nm process.
Even so, TechInsights does not believe that SMIC's N+3 fabrication process is truly equivalent to the 5nm process from TSMC, Samsung, etc. Instead, this process falls somewhere in between 7nm and 5nm nodes.
In fact, the semiconductor-focused research company believes that SMIC's N+3 process, as found within the Kirin 9030 chip, represents an incremental stretch of its existing 7nm node, achieved by leveraging DUV-based multi-patterning and Design Technology Co-Optimization (DTCO) techniques.
For the benefit of those who might not be aware, Deep Ultraviolet (DUV) lithography uses ultraviolet light with a wavelength of 193 nanometers (nm) to etch patterns onto a silicon wafer. By repeating these etching steps, DUV-based multi-patterning techniques can create more intricate circuits.
Similarly, DTCO is an advanced technique that seeks to optimize chip design, manufacturing processes, and yield management simultaneously rather than in the form of discrete steps to achieve feature sizes that would have only been possible otherwise with EUV-based lithography.
When DTCO is used in conjunction with multi-patterning, the resulting flows seek to reduce the impact of process variations and edge placement errors (EPE) that become progressively acute as aggressive DUV multi-patterning progresses.
Coming back, TechInsights believes that the Kirin 9030's N+3 fabrication process did not feature much improvement in fin pitch (FP), contacted poly pitch (CPP), and fundamental transistor geometry that together constitute Front-End-of-Line (FEOL) lithography, which deals primarily with the creation of transistors.
Instead, SMIC's N+3 process appears to have relied mainly on Back-End-of-Line (BEOL) lithography, which deals with building interconnects between transistors, to achieve incremental advancements.
However, this approach has sizable risks as scaling BEOL with DUV requires several patterning steps that must align extremely precisely, or the yields collapse abruptly. What's more, each patterning step adds to line roughness (via misalignment) and defect risk.
Critically, Kirin 9030 shows that SMIC is focusing less on trying to shrink its lithographic processes and more on achieving superior design discipline via DTCO, which has a relatively shallow depth. After all, there is only so much improvement one can extract from such optimizations.
SMIC can still extract sizable performance improvements via advanced packaging techniques, but these are less important for mobile-focused Application Processors (APs) such as the Kirin 9030.
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