It is widely known now that Apple is designing its bespoke server chip in collaboration with Broadcom. While the chip is expected to leverage TSMC's fabs for actual production, a new tidbit suggests Apple might rope in Intel for back-end packaging.
Apple's bespoke AI server chips to use Intel's EMIB packaging as TSMC's CoWoS capacity is choked
We already know two things: Intel's 18A/14A processes are shaping up to be very competitive nodes, and the real constraint with TSMC at the moment lies with its choked CoWoS supply.
For the benefit of those who might not be aware, TSMC's CoWoS (Chip-on-Wafer-on-Substrate) is an advanced chip packaging solution that stacks multiple chips - including CPUs, GPUs, and High Bandwidth Memory (HBM) - onto a silicon interposer for an efficient integration of the entire package.
Now, GF Securities Hong Kong (GFHK) has just published an interesting note, declaring that Intel is expected to "benefit from the CoWoS undersupply of TSMC."
The report reiterates that Apple is currently evaluating Intel's 18A-P process for its lowest-end M-series chips that are expected to ship in 2027. We noted recently that Apple has already signed an NDA with Intel and procured PDK samples of its advanced 18A-P process for evaluation purposes.
Interestingly, the report also notes that bespoke ASICs from Apple and Broadcom will use Intel's EMIB packaging technology in 2028.
Back in Spring 2024, multiple reports emerged that Apple was working with Broadcom on its first AI server chip, bearing the internal codename "Baltra," with actual shipments slated for 2027. The latest note from the Hong Kong-based brokerage house, however, suggests that Apple will only be able to ship its bespoke AI server chips by 2028.
Meanwhile, GF Securities is already on the record for stating that Apple might adopt Intel's 18A-P process for its non-Pro iPhone chips shipping in 2028. Do note that Intel's 18A-P process is its first node to support Foveros Direct 3D hybrid bonding, which allows for stacking multiple chiplets through TSVs.
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