AMD Unveils 5th Gen EPYC “Turin” CPUs: Up To 192 “Zen 5” Cores, 384 Threads On SP5 Socket & Coming 2H 2024

Jun 2, 2024 at 10:43pm EDT

AMD has officially unveiled its next-gen EPYC 9005 "Turin" CPU family which brings up to 192 Zen 5 cores in the second half of 2024.

AMD Goes Big With Next-Gen EPYC Turin CPUs, Up To 192 Cores & 384 Threads To Dominate The Data Center Segment

AMD has finally lifted the curtains off its next-gen Data Center powerhouse, the Zen 5-based EPYC Turin CPU which is expected to be branded under the EPYC 9005 family and feature a diverse range chips ranging from compute, cloud, telco, edge optimized variants. AMD isn't giving us any specifics at the moment but what they are telling us is that Intel should be very afraid of what's coming since Turin looks like a monster!

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In terms of performance, AMD stacks a 128-core EPYC "Turin" CPU against an Intel 5th Gen Xeon Emerald Rapids CPU, the Xeon Platinum 8592+, with 64 cores since as high as Emerald Rapids go. The AMD Turin CPUs offer anywhere from 2.5x to 5.4x gains in performance across various work loads which is very impressive.

The preliminary specifications of AMD's next-gen EPYC Turin lineup which will be branded under the 5th Gen EPYC family were also revealed a while back and included at least 20 SKUs based on the Zen 5 & Zen 5C core architecture. The CPUs are designed to feature drop-in compatibility with the existing 4th Gen EPYC family on the SP5 (LGA 6096) socket and will feature support for faster DDR5 6000 MT/s memory too. The lineup is going to feature up to 128 Zen 5 and 192 Zen 5C cores so starting with that let's take a look at the SKUs.

So far, we have seen SKUs such as the EPYC 9845 (160 Core / 320 Thread), 9825 (144 Core / 288 Thread), 9745 (128 Core / 256 Thread), 9655 (96 Core / 192 Thread), 9645 (96 Core / 192 Thread), and 9565 (72 Core / 144 Thread). All of these SKUs are 64 Core+ variants and feature more than 256 MB of L3 cache and TDPs ranging from 320/400 up to 500W. Following are the various CPU configurations that we should expect in the EPYC Turin family:

Now since it isn't mentioned if these are Zen 5 or Zen 5C SKUs, the cache pools range from 256 MB and up to 384 MB. For the 96-core SKU, if it is based on the Zen 5 architecture, then it should carry an impressive 512 MB of L3 cache but if it's based on the Zen 5C architecture, then it should retain a 256 MB cache.

The rest of the lineup is pretty much the standard 8, 16, 24, 32, 36, 48, 64 core affair with standard and Frequency-optimized offerings. The clock speeds range from as low as 2.0 GHz to up to 4 GHz (base) while the TDPs range from 155W/200W/210W/280W &300W+. AMD's EPYC Turin CPUs will support up to DDR5-6000 MT/s memory in up to 4 TB capacities on an 8 DIMM motherboard, offering up to 128 PCIe Gen5 lanes.

The AMD EPYC Turin "5th Gen" family for servers is expected to debut later this year after the formal launch of Zen 5 & Zen 5C architectures for the desktop and client PC platforms such as Granite Ridge and Strix Point. The 5th Gen EPYC Turin family will be competing against Intel's Xeon Granite Rapids P-Core and Sierra Forest E-Core (288 Core) CPUs. AMD recently confirmed that it is now sampling its 5th Gen EPYC Turin CPUs.

AMD EPYC CPU Families:

Family NameAMD EPYC VeranoAMD EPYC VeniceAMD EPYC Turin-XAMD EPYC Turin-DenseAMD EPYC TurinAMD EPYC SienaAMD EPYC BergamoAMD EPYC Genoa-XAMD EPYC GenoaAMD EPYC Milan-XAMD EPYC MilanAMD EPYC RomeAMD EPYC Naples
Family BrandingEPYC 9007EPYC 9006EPYC 9005EPYC 9005EPYC 9005EPYC 8004EPYC 9004EPYC 9004EPYC 9004EPYC 7004EPYC 7003EPYC 7002EPYC 7001
Family Launch2027202620252025202420232023202320222022202120192017
CPU ArchitectureZen 7Zen 6Zen 5Zen 5CZen 5Zen 4Zen 4CZen 4 V-CacheZen 4Zen 3Zen 3Zen 2Zen 1
Process NodeTBD2nm TSMC4nm TSMC3nm TSMC4nm TSMC5nm TSMC4nm TSMC5nm TSMC5nm TSMC7nm TSMC7nm TSMC7nm TSMC14nm GloFo
Platform NameSP7SP7SP5SP5SP5SP6SP5SP5SP5SP3SP3SP3SP3
SocketTBDTBDLGA 6096 (SP5)LGA 6096 (SP5)LGA 6096LGA 4844LGA 6096LGA 6096LGA 6096LGA 4094LGA 4094LGA 4094LGA 4094
Max Core CountTBD9612819212864128969664646432
Max Thread CountTBD19225638425612825619219212812812864
Max L3 CacheTBDTBD1536 MB384 MB384 MB256 MB256 MB1152 MB384 MB768 MB256 MB256 MB64 MB
Chiplet DesignTBD8 CCD's (1 CCX per CCD) + 2 IOD?16 CCD's (1CCX per CCD) + 1 IOD12 CCD's (1CCX per CCD) + 1 IOD16 CCD's (1CCX per CCD) + 1 IOD8 CCD's (1CCX per CCD) + 1 IOD12 CCD's (1 CCX per CCD) + 1 IOD12 CCD's (1 CCX per CCD) + 1 IOD12 CCD's (1 CCX per CCD) + 1 IOD8 CCD's (1 CCX per CCD) + 1 IOD8 CCD's (1 CCX per CCD) + 1 IOD8 CCD's (2 CCX's per CCD) + 1 IOD4 CCD's (2 CCX's per CCD)
Memory SupportTBDDDR5-12800DDR5-6000?DDR5-6400DDR5-6400DDR5-5200DDR5-5600DDR5-4800DDR5-4800DDR4-3200DDR4-3200DDR4-3200DDR4-2666
Memory ChannelsTBD16-Channel (SP7)12 Channel (SP5)12 Channel12 Channel6-Channel12 Channel12 Channel12 Channel8 Channel8 Channel8 Channel8 Channel
PCIe Gen SupportTBD128-192 PCIe Gen 6TBD128 PCIe Gen 5128 PCIe Gen 596 Gen 5128 Gen 5128 Gen 5128 Gen 5128 Gen 4128 Gen 4128 Gen 464 Gen 3
TDP (Max)TBD~600W500W (cTDP 600W)500W (cTDP 450-500W)400W (cDP 320-400W)70-225W320W (cTDP 400W)400W400W280W280W280W200W

About the author: A Software Engineer by training and a PC enthusiast by passion, Hassan Mujtaba serves as Wccftech's Senior Editor for hardware section. With years of experience in the industry, he specializes in deep-dive technical analysis of next-generation CPU and GPU architectures, motherboards, and cooling solutions. His work involves not only breaking news on upcoming technologies but also extensive hands-on reviews and benchmarking.

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