AMD's high-end Ryzen "Strix Halo" APUs have once again been spotted in a shipping manifesto with up to 120W TDP.
More AMD Ryzen "Strix Point" APUs Spotted In Shipping Manifestos With Up To 64 GB Capacities
The shipping manifestos were spotted at nbd.ltd by @harukaze5719 and include several shipments of the same chip which are expected to have been sent for evaluation and testing purposes. These manifestos also reveal the Maple DAP reference evaluation platform which comes in 32 GB and 64 GB memory capacities. Do note that these are not on-package memory modules like the one we'll see with Lunar Lake CPUs but rather on the reference platform themselves since they come with pre-soldered memory.
The AMD Ryzen "Strix Halo" APUs listed here are 120W which is in line with its maximum TDPs that are expected to hit up to 130W. The reference evaluation platform is based around the FP11 board platform.
AMD Strix Halo, A Revolutionary Ryzen APU For The Client Segment
The AMD Strix Halo APUs will be the chiplet offerings, utilizing up to 3 dies, 2 CCDs, and 1 GCD. The chips will feature up to 16 Zen 5 cores with 32 threads. These chips will retain the same L1 and L2 cache structure so that's a maximum of 16 MB L2 cache while the L3 cache will be increased to 32 MB per CCD. So we can see up to 64 MB of L3 cache on the top (two CCD) chips. The CCDs are said to be different than the ones used on Granite Ridge. Also, only the GCD is mentioned which means that there might be no IOD on board the package.
For the iGPU side, the Strix Halo APUs will retain the RDNA 3+ graphics architecture but will come equipped with 20 WGPs or 40 Compute units. Additionally, to support such high-end iGPUs on a chiplet design, there will also be an additional 32 MB of MALL cache onboard the IOD that will be eliminating bandwidth bottlenecks for this uber iGPU.
Other specifications include support for up to LPDDR5x-8000 (256-bit) memory, and an AI "XDNA 2" NPU capable of delivering over 70 TOPs. The Strix Halo APUs will be centered around the latest FP11 platforms. These APUs will feature TDPs of 70W (cTDP 55W) and will support peak ratings of up to 130W.
AMD Ryzen AI HX Strix Halo Expected Features:
- Zen 5 Chiplet Design
- Up To 16 Cores
- 64 MB of Shared L3 cache
- 40 RDNA 3+ Compute Units
- 32 MB MALL Cache (for iGPU)
- 256-bit LPDDR5X-8000 Memory Controller
- XDNA 2 Engine Integrated
- Up To 60 AI TOPS
- 16 PCIe Gen4 Lanes
- 2H 2024 Launch (Expected)
- FP11 Platform (55W-130W)
For display, both AMD Strix and Strix Halo APUs will come with eDP (DP2.1 HBR3) and external DP (DP2.1 UHBR10), USBC Alt-DP (DP2.1 UHBR10) and USB4 Alt-DP (DP2.1 UHBR10) support as a part of their media engines. Strix Halo will feature up to DP2.1 UHBR20 support.
AMD is expected to formally announce and unveil its next-gen Zen 5 "Ryzen" CPU portfolio at its Computex 2024 keynote so expect more information in less than a month.
AMD Ryzen Mobility CPUs:
| CPU Family Name | AMD Sound Wave? | AMD Bald Eagle Point | AMD Krackan Point | AMD Fire Range | AMD Strix Point Halo | AMD Strix Point | AMD Hawk Point | AMD Dragon Range | AMD Phoenix | AMD Rembrandt | AMD Cezanne | AMD Renoir | AMD Picasso | AMD Raven Ridge |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Family Branding | TBD | Ryzen AI 400 | TBD | TBD | Ryzen AI 300 | Ryzen AI 300 | AMD Ryzen 8040 (H/U-Series) | AMD Ryzen 7045 (HX-Series) | AMD Ryzen 7040 (H/U-Series) | AMD Ryzen 6000 AMD Ryzen 7035 | AMD Ryzen 5000 (H/U-Series) | AMD Ryzen 4000 (H/U-Series) | AMD Ryzen 3000 (H/U-Series) | AMD Ryzen 2000 (H/U-Series) |
| Process Node | TBD | 4nm | 4nm | 5nm | 4nm | 4nm | 4nm | 5nm | 4nm | 6nm | 7nm | 7nm | 12nm | 14nm |
| CPU Core Architecture | Zen 6? | Zen 5 + Zen 5C | Zen 5 | Zen 5 | Zen 5 + Zen 5C | Zen 5 + Zen 5C | Zen 4 + Zen 4C | Zen 4 | Zen 4 | Zen 3+ | Zen 3 | Zen 2 | Zen + | Zen 1 |
| CPU Cores/Threads (Max) | TBD | 12/24 | 8/16 | 16/32 | 16/32 | 12/24 | 8/16 | 16/32 | 8/16 | 8/16 | 8/16 | 8/16 | 4/8 | 4/8 |
| L2 Cache (Max) | TBD | 12 MB | TBD | TBD | 24 MB | 12 MB | 4 MB | 16 MB | 4 MB | 4 MB | 4 MB | 4 MB | 2 MB | 2 MB |
| L3 Cache (Max) | TBD | 24 MB + 16 MB SLC | 32 MB | TBD | 64 MB + 32 MB SLC | 24 MB | 16 MB | 32 MB | 16 MB | 16 MB | 16 MB | 8 MB | 4 MB | 4 MB |
| Max CPU Clocks | TBD | TBD | TBD | TBD | TBD | 5.1 GHz | TBD | 5.4 GHz | 5.2 GHz | 5.0 GHz (Ryzen 9 6980HX) | 4.80 GHz (Ryzen 9 5980HX) | 4.3 GHz (Ryzen 9 4900HS) | 4.0 GHz (Ryzen 7 3750H) | 3.8 GHz (Ryzen 7 2800H) |
| GPU Core Architecture | RDNA 3+ iGPU | RDNA 3.5 4nm iGPU | RDNA 3+ 4nm iGPU | RDNA 3+ 4nm iGPU | RDNA 3.5 4nm iGPU | RDNA 3.5 4nm iGPU | RDNA 3 4nm iGPU | RDNA 2 6nm iGPU | RDNA 3 4nm iGPU | RDNA 2 6nm iGPU | Vega Enhanced 7nm | Vega Enhanced 7nm | Vega 14nm | Vega 14nm |
| Max GPU Cores | TBD | 16 CUs (1024 Cores) | 12 CUs (786 cores) | 2 CUs (128 cores) | 40 CUs (2560 Cores) | 16 CUs (1024 Cores) | 12 CUs (786 cores) | 2 CUs (128 cores) | 12 CUs (786 cores) | 12 CUs (786 cores) | 8 CUs (512 cores) | 8 CUs (512 cores) | 10 CUs (640 Cores) | 11 CUs (704 cores) |
| Max GPU Clocks | TBD | 2900 MHz | TBD | TBD | TBD | 2900 MHz | 2800 MHz | 2200 MHz | 2800 MHz | 2400 MHz | 2100 MHz | 1750 MHz | 1400 MHz | 1300 MHz |
| TDP (cTDP Down/Up) | TBD | 15W-45W (65W cTDP) | 15W-45W (65W cTDP) | 55W-75W (65W cTDP) | 55W-125W | 15W-45W (65W cTDP) | 15W-45W (65W cTDP) | 55W-75W (65W cTDP) | 15W-45W (65W cTDP) | 15W-55W (65W cTDP) | 15W -54W(54W cTDP) | 15W-45W (65W cTDP) | 12-35W (35W cTDP) | 35W-45W (65W cTDP) |
| Launch | 2026? | 2025? | 2025? | 2H 2024? | 2H 2024? | 2H 2024 | Q1 2024 | Q1 2023 | Q2 2023 | Q1 2022 | Q1 2021 | Q2 2020 | Q1 2019 | Q4 2018 |
About the author: A Software Engineer by training and a PC enthusiast by passion, Hassan Mujtaba serves as Wccftech's Senior Editor for hardware section. With years of experience in the industry, he specializes in deep-dive technical analysis of next-generation CPU and GPU architectures, motherboards, and cooling solutions. His work involves not only breaking news on upcoming technologies but also extensive hands-on reviews and benchmarking.
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