Japan's Rapidus is advancing with its 2nm process, as for the first time, the node's logic density has been reported, and it's apparently on par with TSMC's N2.
Japan's Rapidus Could Very Well Compete With TSMC in The 2nm Race, As They Achieve Identical Logic Densities
Rapidus has seen massive popularity in the past few months, mainly because the firm is the leading semiconductor entity in Japan. NVIDIA has also expressed interest. The firm is preparing its cutting-edge 2nm node, named '2HP', and according to information shared by @Kurnalsalts, it is revealed that 2HP will feature logic density similar to TSMC's N2, and more importantly, beating Intel's 18A by quite a difference. This shows that Rapidus' node could pan out to be one of the most competitive processes out there, making a wild-card entry into the semiconductor segment.
The information shared reveals that Rapidus 2HP will feature a logic density of 237.31 MTr/mm², being on par with TSMC's N2, which is claimed to be at 236.17 MTr/mm² currently. The user has also shared the cell library involved in reaching this logic density, including an HD (High Density) library, with a cell height of 138 units, on a G45 pitch. Given that both N2 and 2HP are on a similar figure, this shows that both nodes are HD-style cells, which target maximum logic density, and potentially a similar transistor count once the end solution debuts.
Despite Intel having a relatively lower node-size, the firm's 18A density is claimed to be at 184.21 MTr/mm², it's mainly due to the use of HD libraries for benchmarking the 18A, but another interesting factor here is that with the use of BSPDN, Intel occupies some of the front-side metal layers, which is why there's a drop in the density figure in the HD library measurement. Since Intel's focus is on performance/watt metrics, a higher density isn't the end goal of the company, especially since 18A is mainly intended for internal usage.
Now, Rapidus' 2HP density numbers certainly indicate that the firm is making huge moves in the semiconductor industry. More importantly, the Japanese firm has employed single-wafer front-end processing, which is a one-of-a-kind implementation focused on making adjustments to limited production volume and then scaling the improvements for a better end result. The 2nm PDK from the firm will be available to customers in the first quarter of 2026, and based on the initial information, the node looks promising.
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