AMD Zen 6 CPU Core ISA Revealed: AVX512 FP16, VNNI INT8 & More

Nov 8, 2025 at 03:05am EST
AMD Ryzen processor with ZEN 6 text on a golden background.

AMD's next-gen Zen 6 CPU ISA has been revealed in the latest support added to the GCC compiler, alongside the initial family.

AMD Zen 6 CPU Core To Support AVX512, VNNI INT8 & More According To Latest GCC Compiler Support Update

The GCC Compiler has received a new patch titled "Add AMD znver6 processor support," which essentially adds support for AMD's next-gen Zen 6 core architecture.

Related Story Deals So Good, You’ll Regret Missing These: RX 9070 XT Now At $599 And RX 9060 XT 16 GB At Just $339

The patch also reveals initial ISA (Instruction Set Architecture) for the Zen 6 core, which includes:

While AMD already offers AVX512 support on existing Zen architectures, AVX-512 FP16 will further boost the capabilities of future Zen architectures. The architecture will also support VNNI INT8 as part of its new ISA.

In another post, @InstLatX64 has also discovered a new Zen 6 CPU ID, B80F00, which should point toward one of the several Zen 6 families. Currently, Zen 6 is expected to feature the server Venice lineups in two variants, Classic & Dense. The Venice Classic chips have the SP7 "B50F00" SKUs, and the SP8 "B90F00" SKUs. The Venice dense chips have the SP7 "BC0F00" SKUs, and the SP8 "BA0F00" SKUs.

The classic line will feature up to 12 cores per CCX, while the dense line will feature 32 cores per CCX. We know that the Venice lineup will max out at 256 cores, so that's 8 CCXs, and each CCX carries 128 MB on the dense line, so we will get up to 1024 MB of L3 cache.

Besides that, there are at least four client families that will feature the Zen 6 core architecture. These include the high-end AM5 "Olympic Ridge" with up to 24 cores and 48 threads (12 cores & 48 MB L3 per CCX), Gator Range, Medusa Point, and Medusa Halo. All families with an MCM design will leverage the TSMC N2P process node, while monolithic offerings within the Medusa Point and Gator Range APU lines are expected to utilize TSMC N3P/N3C nodes.

AMD's Financial Analyst Day is just a few days away, and while we can expect a few Zen 6 teases, the actual announcements for Zen 6 CPUs are expected to take place next year, starting CES 2026, so stay tuned.

AMD Zen CPU / APU Roadmap:

Zen ArchitectureZen 7Zen 6CZen 6Zen 5 (C)Zen 4 (C)Zen 3+Zen 3Zen 2Zen+Zen 1
Core CodenameTBAMonarchMorpheusNirvana (Zen 5)
Prometheus (Zen 5C)
Persphone (Zen 4)
Dionysus (Zen 4C)
WarholCerebrusValhallaZen+Zen
CCD CodenameTBATBATBAEldoraDurangoTBCBrekenridgeAspen HighlandsN/AN/A
Process NodeTBA3nm/2nm?2nm/3nm3nm4nm6nm7nm7nm12nm14nm
ServerTBAEPYC Venice (6th Gen)EPYC Venice (6th Gen)EPYC Turin (5th Gen)EPYC Genoa (4th Gen)
EPYC Siena (4th Gen)
EPYC Bergamo (4th Gen)
N/AEPYC Milan (3rd Gen)EPYC Rome (2nd Gen)N/AEPYC Naples (1st Gen)
High-End DesktopTBATBATBARyzen Threadripper 9000 (Shamida Peak)Ryzen Threadripper 7000 (Storm Peak)N/ARyzen Threadripper 5000 (Chagal)Ryzen Threadripper 3000 (Castle Peak)Ryzen Threadripper 2000 (Coflax)Ryzen Threadripper 1000 (White Haven)
Mainstream Desktop CPUsTBATBARyzen **** (Olympic Ridge)Ryzen 9000 (Granite Ridge)Ryzen 7000 (Raphael)Ryzen 6000 (Warhol / Cancelled)Ryzen 5000 (Vermeer)Ryzen 3000 (Matisse)Ryzen 2000 (Pinnacle Ridge)Ryzen 1000 (Summit Ridge)
Enthusiast Mobile CPUsTBATBARyzen **** (Gator Range)Ryzen 9000HX (Fire Range)Ryzen 7000HX (Dragon Range)N/AN/AN/AN/AN/A
Mainstream Desktop . Notebook APURyzen AI 500 (Sound Wave)?Ryzen AI 500 (TBA)Ryzen AI 400 (Medusa Point / BB)Ryzen AI 300 (Strix Point)
Ryzen *** (Krackan Point)
Ryzen 7000 (Phoenix)Ryzen 6000 (Rembrandt)Ryzen 5000 (Cezanne)
Ryzen 6000 (Barcelo)
Ryzen 4000 (Renoir)
Ryzen 5000 (Lucienne)
Ryzen 3000 (Picasso)Ryzen 2000 (Raven Ridge)
Low-Power MobileTBATBATBARyzen *** (Escher)Ryzen 7000 (Mendocino)TBATBARyzen 5000 (Van Gogh)
Ryzen 6000 (Dragon Crest)
N/AN/A

News Source: InstLatX64

Follow Wccftech on Google to get more of our news coverage in your feeds.