AMD's brand new Pensando Pollara 400 AI NIC, the first UEC-ready AI NIC, has been detailed at Hot Chips 2025.
AMD Adds 25% Performance With Its 400GbE Pensando Pollara 400 AI NIC, Ultra Ethernet Consortium-Ready
Last year, AMD introduced its latest networking solution, the Pensando Pollara 400, which is a NIC developed for AI systems. This NIC is also the industry's first to be UEC or Ultra Ethernet Consortium-Ready. In terms of bandwidth, the 400 Gbps speed matches that of NVIDIA's ConnectX-7 solution, but they also have a higher-end ConnectX-8 solution shipping with newer Blackwell Ultra systems, offering 800GbE speeds.
Some of the main features of Pensando Pollara include:
- Programmable Hardware Pipeline
- Up To 1.25x Performance Boost
- 400 Gbps
- Open Ecosystem
- UEC Ready RDMA
- Reduction in Job Completion Times
- High Availability
The Pensando Networking solutions are designed in accordance with AMD's other Data Center solutions, such as EPYC and Instinct families. The company relies on PCIe switches that connect to NICs and CPUs.
The Pensando NIC itself doesn't feature any PCIe switch and connects to a Gen5 x16 interface. The following is the block diagram:
AMD relies on a P4 architecture for its Pensando Pollara 400 AI NIC.
Some of the main P4 Pipeline components include the Table Engine or TE which generates table keys from a package header vector, hash, or directly. It also issues memory reads based on the type.
The P4 architecture also includes an MPU or Match Processing Unit, which is a domain-specific processor with efficient opcodes for field manipulation by the compiler, and offers separate memory, table, and PHV interfaces.
Some enhancements include Virtual Address to Physical Address (va2pa) with address translation capabilities.
Atomic memory operations have also been implemented adjacent to the SRAM.
The Pipeline Cache Coherency is handled by invalidate/update logic, and enables P4 coherency on an address range basis.
Some of the challenges associated with driving AI system performance on Scale-out networks are also shared. These include poor link utilization from ECMP load balancing, network and node congestion, and network packet loss (to name a few).
AMD also shares the percentage of time spent in networking using back-end networks. These are time losses.
AI networks have higher network utilization rates than General general-purpose networks, usually saturating the entire network bandwidth. AMD discusses some of these challenges and their solutions.
The main solution to these challenges comes in the form of adopting UEC or Ultra Ethernet Consortium, which is an open, interoperable, high-performance, and full-communications stack architecture to meet the networking demands of AI and HPC at scale. It's performant, scalable, and cost-effective.
AMD's Pensando Pollara 400 AI UEC-Ready RDMA NIC offers a 25% performance gain against RoCEv2 4 Qpairs and 40% improvement versus RoCEv2 1 Qpair.
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