Open Silicon Announces The World’s First HMC 2.0 Controller IP – Partners Include Altera and Intel

Usman Pirzada

Open-Silicon recently announced the HMC 2.0 (Memory) Controller IP and known partners (not listed in the Press Release) such as Intel are going to be implementing the new design in their future semi conductor products. This latest standard (HMC 2.0) will probably be featured in Intel's Xeon Phi and certain Altera FPGA/SoCs.

Altera Stratix 10 HMC SoCA slide from Altera showing HMC integration into FPGAs and SoCs @Altera Public Domain

HMC 2.0 Controller IP released by Open-Silicon - to be implemented by the HMC Consortium

Open-Silicon is one of the founding members of the Hybrid Memory Cube consortium and is also the one that licenses the use of the memory type. Specifically the difference between HMC 1.0 and HMC 2.0 include a jump from 15Gbit/s to 30Gbit/s (not the total effective throughput of the HMC). Speeds upto 480GB/s are achievable with 1TB/s now in the horizon. The controller supports networking of upto 400Gb/s (increased form 100Gb/s). HMC is currently only available in 2GB and 4Gb variants. Currently each HMC has 4 memory stacks with 1 control die (similar to 4+1 or 4 Hi HBM) and TSVs are used to connect them.

“Stacked DRAM and logic solutions, such as HMC 2.0, break through the memory bottleneck and deliver the performance and low-power needed by next-generation computing systems,” said Jim Handy, memory analyst with Objective Analysis. “Integration-ready interface solutions like Open-Silicon’s HMC controller IP should drive down the cost of deployment, and accelerate this transition.” The Open-Silicon HMC 2.0 memory controller IP is a licensable, soft macro implementation that is designed to be compliant with both HMC v1.0 and the upcoming HMC v2.0, supporting all of the defined data rates of both standards.

The device seamlessly interfaces to leading third-party SerDes IP without the need for an additional PCS layer. Moreover, Open-Silicon’s recently announced SerDes Technology Center of Excellence (TCoE) will provide ASIC customers a convenient and reliable way to verify and test the integration of the HMC 2.0 memory controller IP with SerDes. Supporting data rates of up to 480 GBytes/s, the IP offers a low latency and a flexible user interface. The IP is delivered with a comprehensive set of deliverables including a test bench with a generic HMC model. For more information about the Open-Silicon HMC 2.0 controller, please visit or e-mail us at

Needless to say this is just one more step towards the mass implementation of the Hybrid Memory Cube standard in everyday products. For the time being however only graphic and data accelerators are going to use this with the mainstream segment occupied by JEDEC's High Bandwidth Memory. Nvidia and AMD are both going to be utilizing HBM in their future GPUs however professional accelerators such as Tesla might shift to HMC instead.

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