Intel’s Rumored 3 Million TPU Win For Google Gets Cold Water From JPMorgan, Which Calls It A ‘Storm In A Teacup’

Jun 9, 2026 at 04:20pm EDT

After a report from The Information claimed that Intel would manufacture Google's custom AI chips called tensor processing units (TPUs), analysts at Citi and JPMorgan have shared their thoughts on the matter. Intel's foundry business and its EMIB-T packaging technology have been at the center of supply chain rumors lately as Google's cooperation with it and capacity constraints at TSMC set it up as an alternative to the Taiwanese firm's technology. However, JPMorgan believes that the chips discussed in the report will still be manufactured by TSMC, with Intel responsible for the packaging.

Citi & JPMorgan Share Thoughts On Whether Intel Will Manufacture Google's TPUs

The Information's report created quite a bit of a stir as it claimed that Google had placed an order with Intel to manufacture three million TPU chips. The report was the first of its kind to make the claim, as earlier reports had simply pointed towards the partnership between the two for packaging technology. Packaging, in semiconductor manufacturing, refers to the final assembly of a chip where its different components are assembled.

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Intel's EMIB-T offers a low-cost alternative to TSMC's high-end CoWoS technology and is preferred primarily by lower-power custom AI chips. However, investment bank JPMorgan believes that, unlike The Information's claims, the partnership between Intel and Google is limited to packaging instead of chip fabrication.

In its coverage of the report, JPMorgan remarks that the coverage "seems like a storm in a teacup/nothing clearly new." It adds that while companies such as Google might be considering Intel as a backup for their AI chip manufacturing, given the tight capacity at TSMC, there is little evidence provided to back up these claims. The bank then directly targets the claim of three million TPUs being manufactured at Intel to outline that "these chips are still being fabbed at TSMC," with the fab using the 2-nanometer process for the compute die and the 3-nanometer process for the input-output die.

Along with JPMorgan, Citi also discussed the report. In its comment, the bank remarks that while most of the buyside believes that the report covers packaging, its Taiwan semiconductor analyst, Laura Chen, believes that the report can cover Intel's foundry and design services along with the EMIB-T packaging technology.

About the author: Ramish is a seasoned technology writer and editor with more than a decade of experience. He specializes in semiconductor fabrication and market analysis. With a background in finance and supply chain management - via his bachelors in Finance and a micromasters in supply chain management from MIT - Ramish combines financial rigor with deep industry insight to deliver accurate and authoritative coverage.

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