Intel Xeon Phi Knights Landing Processors to Feature ‘Onboard’ Stacked DRAM – Supercharged Hybrid Memory Cube (HMC) upto 16GB

Intel's Xeon Phi Co-Processors are one of the more interesting HPC solutions out there right now (in my personal opinion), partly because they come in a GPU (and now in a CPU) form factor from a company that primarily produces CPUs, and partly because their design is incredibly innovative. So we have received a new leak courtesy of the reliable Chinese VR-Zone on these co-processors.

16GB Hybrid Memory Cube will Supercharge the 14nm 'Knights Landing' Intel Xeon Phi Co-Processors

As you may recall the codename of the upcoming "Xeon Phi" Processors is 'Knights Landing'. The architecture is the improved version of 'Silvermont' which coincidentally was also used in Atom processors so you can get the idea of the kind of power efficiency we are talking about here. This is also a big upgrade over the Pentium cores used in the Knight's Corner which are the last generation of Xeon Phi Co-processor. Unlike the Hyper Threading technology used in Intel's Core processors,here every Core has 4 virtual threads. Since the flagship will have 72 cores that translates to a massive 288 threads. The leak states that on-package stacked DRAM will be used to improve performance. The codename shown is MCDRAM translates to 'Memory Cube' DRAM aka the Hybrid Memory Cube from Micron.


Now apparently the on-packed stacked DRAM will come in a whooping 16 GB while there are connections for an additional 384 DDR42400Mhz memory.  That is a massive massive amount of memory to have onboard. However there is a technical catch (note the keyword technical). The HMC will not actually be placed or stacked upon the die. It will actually be surrounding the Knights Landing die using a Micron-Intel custom made, super-high bandwidth, parallel path interface that will make the HMC appear as if its on the die. Infact, Intel has stated that "To the programmer, the Micron memory will be transparent to the outside world--almost like a layer three cache inside the package with the processor". So there you go folks, an L3 cache worth 16GB. Ofcourse if you strip away the marketing material you would realize that an L3 cache is faster than the currently known speeds of HMC depending on which processor you have.

The Hybrid Memory Cube used in the Knights Landing Xeon Phi package will feature upto 2000 TSVs (Through Silicon Vias) and an ASIC at the base of the HMC to manage the DRAM package. It promises more than 5 times the bandwidth of DDR4 RAM and more than 15 times the bandwidth of DDR3 Ram. Because Intel is using a customized Micron 16GB HMC solution (they already have 2GB and 4GB variants) and a customized interface the bandwidth will be 500GB/s. There are also some rumors flying around that the Intel is having troubles with yield. Which is something to be expected considering the exponentially larger die size of Knights Landing compared to the average Intel CPU. And I forgot to mention, the HMC details come from eetimes.

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