AMD Announces 2014-2016 Roadmap – 20nm Project SkyBridge and K12 64-bit ARM Cores For 2016
AMD has just announced their Opteron roadmap for 2014-2016 at the Core Innovation conference which unveils the upcoming Project Skybridge and K12 architecture based family of APUs and SOCs. The new roadmap reveals the ambidextrous design framework which brings computing to several form factors in the dense server market.
AMD Announces 2014-2016 Roadmap – 20nm Project SkyBridge
The Project Skybridge is AMD’s next generation ambidextrous computing architecture that allows x86 Cores and ARM cores to be pin-to-pin compatible allowing the motherboard to run off both SOCs and APUs. The Project Sky-Bridge will feature the new family of APUs and SOCs based on the low-power 20nm Cortex A57 cores with AMD’s GCN core architecture. In simple terms, the Project SkyBridge will allow these low-power ARM based SOCs to run on the same motherboards as the x86 low-power SOCs which will feature AMD’s upcoming Puma+ cores which were recently introduced as a part of the AMD Mullins and Beema APUs. Theses ARM SOCs will also be among the first to feature full support for Android OS platform which AMD hasn’t achieved till now. So this could mean that AMD will soon entering the mobile sector as technology becomes more favorable for the small form factor based products.
The Project SkyBridge APUs and SOCs will be designed with full support for HSA (Heterogeneous System Architecture) in mind and will be available starting in 2015 with families based on both 20nm APUs and SOCs with pin compatible x86/ARM compute. These chips will be developed for several applications such as Dense Server, Embedded, Semi-Custom and Ultra-Low Power Client platforms.
Moving in 2016, AMD would unveil their next generation K12 ARM Core which will be exclusively developed by AMD for AMD and feature the latest 64-bit ARM cores elevating 64-bit ARM performance to new levels. These K12 ARM APUs/SOCs will be developed alongside new 64-bit x86 Cores from AMD for their current non-ARM APU lineup.
“We have the world’s best graphics. We know how to do high-frequency designs; we know how to do high-efficiency designs … We can extend the range that ARM’s in – that’s a nice play for us” Jim Keller, AMD
This new ARMv8 CPU core which has been codenamed K12 is being developed under the leadership of chip guru Jim Keller. In an earlier report, Lisa Su (SVP and General Manager of Global Business Units) did mention that they will be going 20nm in 2015 and FinFET after that so its pretty clear that AMD’s K12 core would be based on a 16/ 14nm FinFET process.
Lisa Su – SVP and General Manager of Global Business Units
Sure, Chris. So let me take that and give you a little bit of our thinking.
So in terms of product and technology selection, certainly we need to be at the leading-edge of the technology roadmap. So what we’ve said in the past is certainly this year all of our products are in 28-nanometer across both, you know, graphics client and our semi-custom business. We are, you know, actively in the design phase for 20-nanometer and that will come to production. And then clearly we’ll go to FinFET. So that would be the progression of it.
The ARM K12 Cores would be targeted towards server, embedded and semi-custom markets so its clear that AMD is once again looking for the dense market to make an approach for the new APUs/SOCs.
AMD K12’s x86 Counterpart Also Under-Development
In addition to the K12 which is solely a 64-bit ARM core designed by AMD, the company is also developing a x86 variant of the 64-bit core that would be built from the ground up. AMD’s top chip architect, Jim Keller revealed this during the press conference however no timeframe or codename for the product were revealed. The core’s expected to launch in 2016-2017.
Several details of the upcoming server-aimed chips were leaked prior to the conference which showed that the Toronto APU which is the closest thing we have detailing the specifications of AMD’s 2015 APU codenamed Carrizo. AMD’s Carrizo APU have been detailed by us on several occasions and this confirms most of the information we have been detailing for the past few months. Toronto APU, just like the Berlin APU before it would provide us the details of the specifications AMD’s consumer APU would feature that is codenamed Carrizo.
Powering the CPU side are four x86 Excavator modular cores which leverage the IPC for greater performance compared to Steamroller. The exact percentages are not known at this point by the improvement is rumored to be around 30% which is phenomenal for a new architecture from AMD. Ofcourse we still don’t know that what process the Excavator architecture is based on but previous reports point out to 20nm. On the GPU side, we have the Volcanic Islands core which is a great plus point for this level of APU.
You should keep in mind that the Volcanic Islands graphics isn’t the codename for AMD’s Radeon R200 lineup but infact used to denote their flagship Hawaii based chips. This is a key hint that AMD’s next generation flagship parts would have the same improved GCN 2.0 architecture currently fused only inside the Hawaii chips which feature true AMD Mantle, AMD TrueAudio and AMD OpenCL optimizations. Another plus is that AMD would be shipping Carrizo with both DDR3 and DDR4 memory support so its highly possible that Carrizo would feature support on FM2+ boards with DDR3 memory and also a new socket that would allow DDR4 memory support. Both Toronto and Carrizo APU would share this foundation plus featuring support for PCI-Express 3.0 and HSA.
The Toronto APU and CPU variants would be available in BGA and SOC variants where the SOC variants would have the southbridge planted on the APU die itself. This saves both power and space and optimizes workload offering a more coherent architecture approach which AMD’s HSA is all about. It was said during the AMD presentation that a complete system with the Toronto APU would have a max power usage of 70W.
On the low-end side, we have Seattle CPU powering the 1P clusters with 4-8 ARM Cortex A57 cores and DDR3/4 memory support and Cambridge CPU replacing it in 2015 with 64-bit ARM cores. These are some good additions to the lienup but AMD still needs a true high-end desktop platform to replace their much outdated Vishera CPUs which unfortunately isn’t going to happen in the near future.
AMD’s ambidextrous computing roadmap includes:
- “Project SkyBridge” – This design framework, available starting in 2015, will feature a new family of 20 nanometer APUs and SoCs that are expected to be the world’s first pin-compatible ARM and x86 processors. The 64-bit ARM variant of “Project SkyBridge” will be based on the ARM Cortex-A57 core and is AMD’s first Heterogeneous System Architecture (“HSA”) platform for Android; the x86 variant will feature next-generation “Puma+” CPU cores. The “Project SkyBridge” family will feature full SoC integration, AMD Graphics Core Next technology, HSA, and AMD Secure Technology via a dedicated Platform Security Processor (PSP).
- “K12” – A new high-performance, low-power ARM-based core that takes deep advantage of AMD’s ARM architectural license, extensive 64-bit design expertise, and a core development team led by Chief CPU Architect Jim Keller. The first products based on “K12” are planned for introduction in 2016.
|AMD Trinity APU||AMD Richland APU||AMD Kaveri APU||AMD Berlin APU||AMD Carrizo APU||AMD Toronto APU|
|Core Architecture||x86 Piledriver||x86 Piledriver||x86 Steamroller||x86 Steamroller||x86 Excavator||x86 Excavator|
|GPU Architecture||VLIW4||VLIW4||Sea Islands||Sea Islands||Volcanic Islands||Volcanic Islands|
|GPU Branding||Radeon HD 7000||Radeon HD 8000||Radeon R7 Series||Radeon R7 Series||Radeon R9 Series?||Radeon R9 Series?|
|Memory / HSA Support||DDR3 / No||DDR3 / No||DDR3 / Yes||DDR3 / Yes||DDR3 / DDR4 / Yes||DDR3 / DDR4 / Yes|
|Launch||October 2012||June 2013||January 2014||2014||2015||2015|