The Xeon Phi Co-Processor is a brute beast and Intel’s top of the line high-performance compute accelerator which has been integrated in the world’s fastest supercomputer, the Guangzhou’s Tianhe 2. Around 48,000 units of the Co-processor have been featured inside the 100 Peta Flop cruncher and would soon be added to NASA’s own supercomputer and a few others.
Intel Xeon Phi ‘Knights Landing’ Architecture Detailed
So, the Intel Xeon Phi (previously known as the Larrabee platform) has found some success in the HPC market and Intel is going to expand their Xeon Phi lineup in mid-2015 with the arrival of the Intel Knights Landing, their next generation Xeon Phi Co-processor. VR-Zone has some interesting slides to share regarding the new Intel Xeon Phi Knights Landing Co-processor which show the power and features the new architecture packed abroad the new Xeon Phi.
For starters, we already know that the Xeon Phi ‘Knights Landing’ will be available in two form factors. One as a standalone CPU which could be equipped across multiple sockets in dense servers to pump out Petaflops Compute performance and the second as the PCI-Express Co-Processor which would be available later on. These chips will have a direct interconnect path of 100 GB/s with other Xeon Phi and Xeon processors and are very similar to the normal processors in terms of usage except these will never end up in households but focused strictly towards the HPC and Server market.
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The architectural details are quite interesting since we knew that the Intel Xeon Phi Knights Landing was going to feature a 14nm architecture but instead of the Broadwell cores, the Knights Landing would feature Silvermont cores that are also being featured on Intel’s next generation Atom processors. I believe these are the updated Airmont cores which are a die-shrink of Silvermont based on a 14nm die process. Nevertheless, its a huge update over the cores featured in the first iteration of Xeon Phi Co-processors.
Moving on, there are upto 72 Cores based on the Silvermont architecture inside the Knights Landing. Each core is coupled with four threads so that’s 288 threads, two 512-bit vector units per core and 3 times the single threaded performance improvement over Xeon Phi Knights Corner. It supports the AVX-512 instruction set except TSX. The Xeon Phi Knights Landing also features 36 PCI-Express Gen 3 lanes which can be used to support more Xeon Knight Landing Co-Processors, Discrete graphic cards and PCI-E SSDs for storage. All of this is packed in the 14nm Knights Landing chip with a TDP ranging from 160-200W depending on the SKU. The top SKU pumps up 6 TFlops of single precision and 3 TFlops of double precision floating point performance per socketed Knights Landing chip.
For memory, Knights Landing ships with a 6 Channel DDR4 memory controller capable of supporting upto 384 GB of memory with speeds of 2400 MHz. That is relatively higher compared to 16 GB featured on Knights Corner but we are comparing DDR4 against GDDR5 here. Still no issue, since the Knights Landing comes with an additional 8-16 GB of MCDRAM which is stacked 3D Memory on-board the processor die. This low latency and high bandwidth memory provides 500 GB/s sustained memory to the Co-processor. This is 50% faster than the current generation than AMD’s and NVIDIA’s top of the line GPU accelerator options.
Last of all, we have the Knights Landing-F featuring the Cray HPC interconnect controllers which has 100 Gbit/s interconnect speeds and 32 PCI-Express Gen 3 lanes. This would allow multiple interconnect links to a tons of other Xeon CPUs. Slated for 2015, the Xeon Phi Knights Landing sounds like a beast for the HPC market but competitors won’t remain silent since AMD has yet to launch a new FirePro product based on their latest and powerful Volcanic Islands architecture while NVIDIA will be aiming for their Maxwell architecture release next year which would end up in their future line of Tesla and Quadro series cards.