Intel Confirms Launch of 10nm Cannonlake Processors in 2H 2017

Hassan Mujtaba
Posted Feb 20, 2016
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Intel has confirmed to the Motely Fool that they will introduce their first 10nm products in the second half of 2017. The news comes after an erroneous job listing over at Intel’s website led many to believe that the new chips would face major production issues that would lead Intel to delay their Cannonlake generation to 2018 however Intel clarified that the listing has been taken down since it contained error and 10nm chips remain on track.

Intel’s 10nm Cannonlake Processors on Track – Arriving in 2H 2017

Intel has confirmed what the rumor mill had been alleging for some time now that they will launch their 10nm chips in 2H 2017. There’s no doubt that Intel has faced some serious problems with shrinking nodes. The poor yields have been a major issues which have affected the production of chips with smaller process nodes.

After the publication of the article, Intel PR reached out to let me know that the listing itself contained “errors” and that it would be taken down (a quick check shows that it has indeed been removed). Intel further clarified that its “first 10-nanometer product is planned for the second half of 2017.” via The Motely Fool

Due to poor yields and the complexity in achieving smaller nodes, Intel is pushing their 10nm processors ahead to gain process maturity by the time Cannonlake hits the market. However, we have seen this trend since the 14nm Broadwell architecture with which Intel had a really difficult time and was pushed several months back in the desktop and mobility segments. In their past earning calls, Intel did report that their cadence today is closer to 2.5 years than two.

 

In the past, Intel’s Tick-Tock roadmap was simple and clear, they would release a Tick, a new (smaller) process node which will be using an existing architecture with minor updates and that would be followed by a Tock, a brand new microarchitecture built upon an existing process node. This isn’t the case anymore, since it’s getting harder to gain smaller node early, Intel now relies on a third Tock within their Tick-Tock cycle. The third Tock is not a massive architectural update, nor is it a complete refresh of an existing microrchitecture. The Intel 14nm Broadwell CPUs were the Tick, Skylake were the Tock and the upcoming Kaby Lake processors will be another Tock or should we say, Semi-Tock.

“As node transitions lengthened, we adapted our approach to the Tick-Tock method, which gave us a second product on each node. This strategy created better products for our customers and a competitive advantage for Intel. It also disproved the death of Moore’s Law predictions many times over. The last two technology transitions have signaled that our cadence today is closer to 2.5 years than two.

To address this cadence, in the second half of 2016 we plan to introduce a third 14-nanometer product, code named Kaby Lake, built on the foundations of the Skylake micro-architecture but with key performance enhancements. Then in the second half of 2017, we expect to launch our first 10-nanometer product, code named Cannonlake. We expect that this addition to the roadmap will deliver new features and improved performance and pave the way for a smooth transition to 10-nanometers.”

There are several challenges ahead for Intel as competition rises from TSMC who are expected to develop their 7nm node process in 2017 followed by 5nm process node in 2020. Intel’s William Holt, who leads technology and manufacturing group stated that Intel will start looking into new technologies if they want to improve their processors in the future. Holt stated that Moore’s law is a good foundation if they keep on focusing ways to reduce the cost per transistor but they will see a variety of post-CMOS technologies being implemented in the chip architecture itself. These technologies are not confirmed but Intel has cited the use of spintronics and the quantum tunneling methods. However, while these technologies help reduce the overall power and cost per transistor, they also run much slower than CMOS circuits.

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“The economics of Moore’s Law are sound if we focus on reducing cost per transistor,” William Holt told about 3,000 attendees of the International Solid-State Circuits Conference (ISSCC) here. But “beyond CMOS we’ll see changes in everything, probably even in computer architecture,” he said.

“We’re going to see major transitions,” said Holt. “The new technology will be fundamentally different. The best pure technology improvements we can make will bring improvements in power consumption but will reduce speed.”

“I can’t tell you which of these [post-CMOS] technologies will be first or best but when we see this richness [of possibilities]…that provides a wealth of opportunities over the next few years to make the tremendous progress needed in how to architect our parts,” he said.  “It’s your challenge to figure out how to make them,” he told attendees.

“It’s too early to make a prediction on the details of the 7nm node, but we can say we may be more in the range of the historical line of cost per transistor reduction at 7nm — but we see a feasible path to cost reduction,” he said. via EETimes

Regardless, we are still  years away from looking at a 7nm chip from Intel. Intel’s 10nm Cannonlake has been confirmed to arrive in 2H 2017. In 2H 2016, we would see Kaby Lake, the last of the 14nm families from Intel. The Ice Lake processors from Intel which will be succeeding Cannonlake in 2018 are also confirmed along with their refresh which is codenamed “Tiger Lake”.

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