Evidence regarding stacked DRAM on next generation AMD APUs has surfaced once again which gives hints that the upcoming Carrizo APU or its successor will be the first APUs to enable high-bandwidth stacked DRAM design on-chip.
Evidence Regarding AMD APUs Featuring High-Bandwidth Stacked Memory Surfaces
It has been known for a while that AMD is sampling their first generation HBM (High Bandwidth Memory) and we can find official specifications in slides dating back to December 2013. While there was no mention of what product or application may make use of HBM back then, the latest slides from AMD’s official Fast Forward presentation talks regarding stacked DRAM specifically on APUs. The Fast Forward project’s objectives are to enhance the high volume APU architecture and investigate in next generation processor and memory tech for exascale and consume scale systems.
Within the presentation, you can find several references of stacked memory and new APU technologies such as HSA+, PIM (Processing In Memory) and Two Level memory. Some of these are already part of the current AMD APU family such as Kaveri which introduced several new features such as HSA on software and steamroller, gcn or hardware side.