Apple A10 Shows Up In The Latest Image – It’s Based On The FinFET WLP Process
The first real shot of Apple’s A10 SoC that’s going to be present inside an iPhone 7 has been leaked, showing the efficient and powerful chipset that’s going to power up a total of two smartphones that are going to be introduced in September.
A10 Is Manufactured On TSMC’s 16nm FinFET Technology – Dual-Core CPU With High Clock Speed Expected
While the image could easily be concluded as nothing more than a fake, the chipset has been labeled with a 1628 date code, suggesting that it will correspond with the mid-July production.
We have also managed to upload an image what appears to be the alleged benchmarking results of the iPhone 7 Plus. Despite the fact that the processor running inside an iPhone 7 Plus features only two cores, the custom design of the CPU, not to mention the superior architecture contributes impressively to the scores that you see before you. One other element that you might have seen is that the smartphone packs 3GB of RAM according to the specifications, thus giving us further proof that the phablet sized handset will come packing with a nice little memory upgrade.
As you all know, Apple’s A10 is going to be manufactured on TSMC’s 16nm FinFET technology, which is the same node that’s going to be used for the upcoming Apple Watch 2. We know for a fact that all upcoming iPhone 7 models are going to feature an A10 SoC, and according to the leaked performance metrics that we reported before, the chipset was giving us a fair amount of doubt, but it looks like we can feel a lot better now.
The phones could also feature LTE modems from two different companies, and we believe that the phablet is going to feature a 3,100mAh battery, which is huge even by Apple standards, along with on-board storage increased to 256GB. We expect that 256GB will be nice little upgrade for those who have capped their 128GB internal memory (for a premium price obviously).
Apple is also said to adopt a new chip developing technology called FoWLP, which stands for fan-out wafer level packaging platform. With this technology, smartphone OEMs can greatly reduce the thickness of their mobile devices since FoWLP does not require a PCB. Additionally, it is able to increase the efficiency of chips by 30 percent and reduce the thickness of smartphones by at least 0.3mm. We bet Apple’s ears must be ringing when they were pitched that smartphone thickness could be using by employing this technology in mobile devices.
Are you excited to see the A10 SoC in process? Tell us your thoughts right away.