AMD’s Trinity APU Core Upclose; Bigger Than Anticipated

Sabeeh Qureshi
Jan 9, 2012
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SemiAccurate had leaked photos of AMD’s Trinity APU core with only a picture yet no details or whatsoever on the die. However an online PC enthusiast has stepped forward and given out some details of what’s on the chip.

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According to Charlie Demerjian, the Trinity APU incorporates two Piledriver modules that are an enhanced variant of the Bulldozer architecture.

The 4 cores seem to be smaller than its predecessor with a DDR3 memory controller placed on top along with a UVD decoder module. On the other hand, the bottom consists of the Display controller and the Northbridge PCI-E controller. At this point, the overall design looks pretty similar to the Llano APUs.

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Also, the Trinity APU is said to support DDR3 frequencies of 2133 MHz. There is also a possibility of these APUs to come with native PCI-E 3.0 support.

The most critical part of the GPU graphics core has also been detailed and said to have six ‘VLIW4 flow processors’ in an array architecture that accumulates to a total of 384 stream processors. In comparison with the VLIW5 architecture present in the Llano 400 APUs, this structure seems yet more efficient and achieves overall 30% improvement in performance.

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