AMD Explains Power Efficient Design in Next Generation CPUs/GPUs – Carrizo APU to Double Efficiency of Kaveri APU
AMD’s Future of Compute event was conducted recently and had quite a lot of tidbits of interesting information. One such aspect was AMD’s discussion of Power Efficient design in chip architecture. AMD has previously made the claim on many occasions but this is the first time they have gone into so much detail. One or two slides were recycled (with color changes) from their previous press releases but most are new. The slide deck was provided to us courtesy of DG Lee over at IYD.KR.
AMD won’t rely on process shrinkage for power efficiency and achieving ’25x by 2020′
Silicon processors haven’t been on this earth for a very long time. As the disruptive technology was in a primitive state when it first arrived, achieving huge amounts of power efficiency with each successive generation was easy to come by. However, in this decade we have entered the part of the curve where we are getting exponentially decreasing returns on every additional unit of effort. Since a process shrink can put more transistors in the same space and less electricity is required for the transistors to report their states, you get natural power efficiency jumps with every iteration, but optimizing architecture with the same level of gains is another story altogether.
However, as can be seen with the entire 28nm GPU fiasco, reliance on node shrinkage is a very dangerous thing. We have been stuck on 28nm for what, 3-4 years now? Which means that though you can cram more transistors by increasing the die space, you won’t get any more efficient unless you optimize the architecture itself and it is with this context that the event held by AMD starts. They begin of by showing some statistics: what the trend line for power efficiency increase was before and what it is now (post 2000). And here is what AMD is promising; they will beat not only the current trend line but the historical trend line as well by the 2020 mark ( in its mobile division atleast).
AMD talks about the low power units of its Eco system (APUs) and how their inherent architecture enables them for huge power efficiency boost on the software level. They show some CPU-GPU power trading ratios on how workloads can be split between the CPU and GPU portion of an APU for much better heat dissipation and how the unified architecture avoids redundancy in memory/bus allowing conservation of energy. Do keep in mind that 2020 is now pretty close, so AMD is claiming to be able to hit the 25x sweet spot in approximately 5 years. AMD has also charted a graph similar to the compute one which shows how APUs can harness the growth of the GPU while keeping performance serial.
There are a couple of technical details as well explaining AMD’s boost control system (not boosting software that doesn’t benefit from higher clocks), efficient voltage control and power – battery tradeoffs among other things. The biggest way a chip can conserve power is through the Idle state, and some of the slides mention how they can optimize the process so the CPU goes to sleep more easily and quickly. Interestingly they also show the predicted energy efficiency of Carrizo APU which is approximately double that of the Kaveri APU. Not really surprising but still interesting to know. All in all, the slides make a good read.