New AMD Slides Detail Upcoming Radeon HD 79** Series GPU Architecture

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Jun 15, 2011
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AMD has released two slides which details its next generation HD 79** series GPU architecture. The slides were revealed at the AMD’s Fusion developer summit where AMD also officially announced the¬†availability¬†of its Mainstream desktop lineup of Llano APU’s.

Looks like AMD would be ditching the VLIW instruction format and looking forward to move towards the SIMD wide-vector execution. You can check out the brief overview of the Slides along with the screenshots below:

* Ditch the VLIW instruction format and move to SIMD wide-vector execution
* L1 and L2 read / write caching
* Out of order resource allocation
* ECC data protection on SRAMs and global memory
* Parallel primitive

A few highlights from the talk: Multiple primitive pipelines for setup, etc.
Real caching in L1, L2, separate color / z caches for graphics and atomics
Concurrent tasks
Out of order resource allocation
ECC on srams and drams

No VLIW, just multiple issue SIMD
Branch, scalar, vector, vector memory, export units
4×16 wide vector ALUs

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