AMD Unveils FinFET based GCN Optimization with Double the Energy Efficiency and HBM

Usman Pirzada
Posted May 6, 2015
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AMD is currently doing its live analysts day webcast and have unveiled their new GCN revision which will feature some interesting features. Graphics Core Next is AMD’s modern GPU architecture that was launched back in 2012. This particular revision of GCN is basically an implementation that will be based (and optimized for) FinFET process technology and will roughly double the power efficiency of the architecture. At the same time, HBM made an appearance too.

AMD Next Generation Radeon GCN 2015 GPU LineupA slide from the Analysts Day webcast showing the upcoming Radeon 300 Series products.

AMD ups energy efficiency with GCN Optimization and reiterates HBM (memory)

AMD’s analysts day web cast revealed quite a few bits of interesting information about AMD’s various IPs. One of the more relevant updates was the conversation of GCN based on 14/16nm FinFET and High Bandwidth Memory. CEO Lisa Su made it clear that today was not a product launch – it was more of a tech confirmation of what will be included in the upcoming flagship GPUs. Basically, sub 20nm node (for 2016), HBM memory and one helluva launch are all that have been confirmed. Given below is the slide grab from the analyst event which shows Graphic Core Next (GCN)’s evolution throughout its launch to date.

Sadly, the slide doesn’t really reveal alot except confirming the fact that AMD will be shifting to FinFET with their next flagship and the fact that it will have roughly twice the energy efficiency of a planar die. Lisa Su mentioned that the new architecture would be launching along with the flagship Radeon 300 Series products sometime in the current quarter, in the coming weeks (think Computex). Therefore, information is deliberately lacking in this event, but hey, all this rumor-confirmation really helps us sleep at night.

Up next is AMD re-stating facts about HBM (and also confirming its use in its next flagship). We already know quite a lot about HBM. We know that HBM1 is limited to 4GB but with a Dual Link Interposing design, SK Hynix will be able to stack 4x (Dual 1GB HBM modules) via an Interposer (2.5D stacking). The design will have very high performance at low clock speeds and will also be very power efficient as compared to GDDR5.

SK Hynix and Samsung Talk HBM at Hot Chips 28 - Low Cost HBM, HBM2 and HBM3 In The Roadmap

2x 4-HI HBM1 (which should technically be called 8-Hi-Hi according to nomenclature rules) features a 1024-bit interface, two prefetch operations per IO (dual command) and can push 128GB per second per pin. The tRC is 48nm, tCCD is 2ns (1tCK), and VDD is 1.2V.  The 4-Hi HBM2 (generation 2) features a 1024 bit interface, two prefetch operations per IO (dual command), 64 Byte access granularity (=I/O x prefetch) and can push 256 GB per second per pin.

The bandwidth of an HBM equipped card will most probably be either 512 GB/s – 1024 GB/s depending on the combination used. 2.5D is the best option for high performance ASICs currently primarily because 3D stacking would result in a very very bad heat management. Since the memory would be stacked on top of the die, it would become very difficult to control the heat produced from the power hungry chips that are modern GPUs. Needless to say, this generation of GPUs just got very exciting and AMD’s HBM memory appears to be on the cutting edge of Industry technology.

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